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1 ? fn6681.1 isl9109 rf pa 1.5a dc/dc regulator isl9109 is 1.6mhz synchronous step-down regulator with integrated power switches capable of delivering 1.5a output for powering rf power amplifiers in cellular phones. the isl9109 features a standby mode which allows for rapid startup while prolonging battery life. the supply voltage range is from 2.7v to 5.5v allowing the use of a single li+ cell, three nimh cells, or a regulated 5v input. 1.6mhz pulse-width modulation (pwm) switching frequency allows using small external components. it has a flexible operation mode selection of forced pwm mode and skip (low i q ) mode with typical 22a quiescent current for highest light load efficiency to maximize battery life. the isl9109 integrates a pair of low on-resistance p-channel and n-channel mosfets to maximize efficiency and minimize external component count. when in standby, the isl9109 band-gap reference is powered. this assists in a rapid power-up when the en pin is asserted high. other features include soft-start, overcurrent protection, and thermal shutdown. the isl9109 is offered in 8 ld 2mmx3mm dfn package with 0.9mm typical height. the complete converter can occupy less than 1cm 2 area. features ? integrated synchronous buck regulator with up to 95% efficiency ? 2.7v to 5.5v supply voltage ? 1.5a output current ?4.3a quiescent supply current in standby mode ? 22a quiescent supply current in skip (low i q ) mode ? 3% output accuracy ov er temperature/load/line ? selectable forced pwm mode or skip mode ? less than 1a logic controlled shutdown current ? 100% maximum duty cycle for lowest dropout ? soft-start ? peak current limiting, short circuit protection ? over-temperat ure protection ? 8 ld 2mmx3mm dfn ? pb-free (rohs compliant) applications ? single li-ion battery-powered equipment ? rf power amplifier ? cpu power ? pdas and palmtops pinout isl9109 (8 ld 2x3 dfn) top view ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL9109IRZ* 109 -40 to +85 8 ld 2x3 dfn l8.2x3 *add ?-t? suffix for tape and reel. please refer to tb347 for details on reel specifications. note: these intersil pb-free pl astic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 2 3 4 1 7 6 5 8 vin en n/c mode sw gnd fb stby data sheet september 29, 2008 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2008. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6681.1 september 29, 2008 absolute maxi mum ratings (reference to gnd) thermal information vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v en, mode, stby . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vin + 0.3v sw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5v to 6.5v fb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v recommended operating conditions vin supply voltage range . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 1.5a ambient temperature range . . . . . . . . . . . . . . . . . . .-40c to +85c thermal resistance (notes 1, 2) ja (c/w) jc (c/w) 2x3 dfn package . . . . . . . . . . . . . . 55 5.5 junction temperature range. . . . . . . . . . . . . . . . . .-40c to +125c storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. jc , ?case temperature? location is at the center of the exposed metal pad on the package underside. see tech brief tb379. electrical specifications unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specificati ons are measured at the following conditions: t a = +25c, v in = v en = 3.6v, l = 2.2h, c 1 = 10f, c 2 = 10f, i out = 0a (see the?typical applications? on page 7). parameter symbol test conditions min typ max units supply undervoltage lockout threshold v uvlo rising - 2.5 2.7 v falling 2.2 2.4 - v quiescent supply current i vin en = stby = low (shut down) t a = +25c -0.052 a en = stby = hi for 1ms, then en = low, stby = hi (standby) t a = +25c -4.36.0a en = mode = hi, no load at the output - 22 30 a en = hi, mode = low, no load at the output, vfb = 0.75v -3.65.5ma output regulation fb regulation voltage v fb mode = low 0.78 0.8 0.82 v fb bias current i fb vfb = 0.75v - 0.1 - a line regulation v in = v o + 0.5v to 5.5v (minimal 2.7v) - 0.2 - %/v compensation error amplifier trans-conductance design info only - 20 - a/v sw p-channel mosfet on-resistance v in = 3.6v, i o = 200ma - 0.12 0.22 v in = 2.7v, i o = 200ma - 0.16 0.27 n-channel mosfet on-resistance v in = 3.6v, i o = 200ma - 0.11 0.22 v in = 2.7v, i o = 200ma - 0.15 0.27 p-channel mosfet peak current limit i pk v in = 5.5v, l = 3.3h, v out shorted to gnd thru a 50m resistor 1.8 2.1 2.6 a maximum duty cycle - 100 - % pwm switching frequency f s 1.35 1.6 1.75 mhz sw minimum on time mode = low (forced pwm mode) - 80 - ns isl9109
3 fn6681.1 september 29, 2008 soft start-up time t ss stby = 0, en = _/ start-up is considered complete when v out reaches 93% of final target voltage. -1.1- ms stby = 1 for 1ms, en = _/ start-up is considered complete when v out reaches 93% of final target voltage. --60s stby, en, mode logic input low --0.4v logic input high 1.4 - - v logic input leakage current pulled up to 5.5v - 0.1 1 a thermal shutdown thermal shutdown - 160 - c thermal shutdown hysteresis -25-c electrical specifications unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specificati ons are measured at the following conditions: t a = +25c, v in = v en = 3.6v, l = 2.2h, c 1 = 10f, c 2 = 10f, i out = 0a (see the?typical applications? on page 7). (continued) parameter symbol test conditions min typ max units pin descriptions pin # pin name description 1 vin input supply voltage. connect a 10f ceramic capacitor to power ground. 2 en enable pin. enable the output when driven to high. shut down the chip and discharge output capacitor when driven to low. do not leave this pin floating 3 n/c do not connect; leave floating for proper device operation 4 mode mode selection pin. connect to logic high or vin to enable skip mode; connect to logic low or ground for force pwm mode. 5 stby active high enables the band-gap reference. 6 fb buck regulator output feedback pin. connect to the output voltage through voltage divider resistors for adjustable output voltage. 7 gnd system ground. 8 sw switching node connection. connect to one terminal of the inductor. e-pad - exposed pad. it should be connected to ground for proper electr ical performance. for best thermal performance, connect as much copper as possible to this pad, either on the component layer or other layers through thermal vias. typical operating performance figure 1. efficieny vs load current (v out = 3.3v) figure 2. efficiency vs load current (v out = 2.5v) 50 60 70 80 90 100 0 250 500 750 1000 1250 1500 load current (ma) efficiency (%) vin = 5.5v vin = 4.2v vin = 3.8v 50 60 70 80 90 100 0 250 500 750 1000 1250 1500 load current (ma) efficiency (%) vin = 5.5v vin = 4.2v vin = 3.0v isl9109
4 fn6681.1 september 29, 2008 figure 3. efficiency vs load current (v out = 1.8v) figure 4. switching fr equency vs input voltage, (v out = 1.6v, i out = 1a, t a = +25c) figure 5. i q vs v in (mode = v in , stby = v in , en = v in , v out = 1.6v, i out = 0) figure 6. i q vs v in (mode = v in , stby = v in , en = gnd, i out = 0) figure 7. v out vs v in (mode = v in , v out = 1.6v) figure 8. v out vs v in (mode = v in , v out = 2.5v) typical operating performance (continued) 50 60 70 80 90 100 0 250 500 750 1000 1250 1500 load current (ma) efficiency (%) vin = 5.0v vin = 3.3v vin = 2.7v 1.40 1.45 1.50 1.55 1.60 2.7 3.4 4.1 4.8 5.5 input voltage (v) switching frequency (mhz) 0 5 10 15 20 25 30 2.7 3.4 4.1 4.8 5.5 input voltage (v) quiescent current (a) 0 1 2 3 4 5 2.7 3.4 4.1 4.8 5.5 input voltage (v) quiescent current (a) 1.600 1.605 1.610 1.615 1.620 2.7 3.4 4.1 4.8 5.5 input voltage (v) output voltage (v) i out = 500ma i out = 1000ma i out = 0ma 2.50 2.51 2.52 2.53 2.54 2.7 3.4 4.1 4.8 5.5 input voltage (v) output voltage (v) i out = 500ma i out = 1000ma i out = 0ma isl9109
5 fn6681.1 september 29, 2008 figure 9. soft-start (v in = 4.2v, v out = 1.6v, stby = 0v, i out = 500ma) figure 10. soft-start (v in = 4.2v, v out = 1.6v, stby = v in , i out = 500ma) figure 11. steady-state in skip mode (v in = 5.0v, v out = 1.8v, i out = 35ma) figure 12. steady-state in pwm mode (v in = 5.0v, v out = 1.8v, i out = 1.2a) figure 13. steady-state in skip mode (v in = 5.0v, v out = 3.3v, i out = 35ma) figure 14. steady-state in pwm mode (v in = 5.0v, v out = 3.3v, i out = 1.2a) typical operating performance (continued) 5v/div vout 5v/div sw 2v/div en 200s/div 5v/div vout 5v/div sw 2v/div en 10s/div 1 s/div 200ma/div 2v/div v out (ac coupled) v sw 20mv/div i l 1 s/div 1a/div 20mv/div 2v/div v out (ac coupled) v sw i l 4 s/div 200ma/div 50mv/div 2v/div v out (ac coupled) v sw i l 1 s/div 1a/div 20mv/div 2v/div v out (ac coupled) v sw i l isl9109
6 fn6681.1 september 29, 2008 figure 15. load transient test (mode=gnd v in = 5.0v; v o = 1.5v; i o = 0.01a~1a) figure 16. load transient test (mode = gnd, v in = 3.6v; v o = 1.5v; i o = 0.01a~1a) figure 17. load transient test (mode = gnd, v in = 3.6v; v o = 2.5v; i o = 0.01a~1a) figure 18. load transient test (mode = v in = 5v; v o = 3.3v; i o = 0.2a~0.4a) typical operating performance (continued) 100 s/div 1a/div 100mv/div 2v/div v out (ac coupled) v sw i l 100 s/div 1a/div 100mv/div 2v/div v out (ac coupled) v sw i l 100s/div 1a/div 100mv/div 2v/div v out (ac coupled) v sw i l 100s/div 0.5a/div 50mv/div 2v/div 0.2a/div v out (ac coupled) v sw i l i out isl9109
7 fn6681.1 september 29, 2008 typical applications figure 19. typical application diagram parts description manufacturers part number specifications size l inductor toko 1098as-2r0am 2.0h/1.8a/67m 3.0mmx3.2mmx1.2mm c 1 input capacitor murata grm21br60j106ke19l 10f/6.3v 2.0mmx1.25mmx1.25mm c 2 output capacitor murata grm21br60j106ke19l 10f/6.3v 2.0mmx1.25mmx1.25mm c 3 capacitor murata grm1885c1h121ja01d 120pf/50v 1.6mmx0.8mmx0.8mm r 1 , r 2 resistor various 100k , smd, 0.5% 1.6mmx0.8mmx0.45mm isl9109 sw gnd fb stby vin en n/c mode e-pad input 2.7 to 5.5v 10f 10f 120pf 100k 100k 1.6v, 1.5 output c1 c2 c3 r1 r2 2.0h isl9109
8 fn6681.1 september 29, 2008 block diagram figure 20. functional block diagram sw + + csa + + ocp vref1 skip + + soft start 0.8v eamp comp pwm/pfm logic controller protection driver fb n/c mode shutdown vin gnd bandgap scp + en shutdown stby vref2 vref3 zero-cross sensing slope comp oscillator + isl9109
9 fn6681.1 september 29, 2008 theory of operation the isl9109 is a step-down switching regulator optimized for battery-powered handheld applications. the regulator operates at a typical 1.6mhz fixed switching frequency under heavy load conditions to allow small external inductor and capacitors to be used for minimal printed-circuit board (pcb) area. at light load, the regulator can be selected to enter skip mode to reduce the switching frequency. unless forced to the fixed frequency, to minimize the switching loss and to maximize the battery life. the quiescent current under skip mode, with no loading is typically only 22a. the supply current is typically only 4a in standby mode, and 0.05a when the regulator is in shutdown mode. pwm control scheme the device uses the peak-c urrent mode pulse-width modulation (pwm) control sc heme for fast transient response and pulse-by-pulse current limiting. figure 20 shows the circuit functional block diagram. the current loop consists of the oscillator , the pwm comparator comp, current sensing circuit, and the slope compensation for the current loop stability. the current sensing circuit consists of the resistance of the p-channel mosfet when it is turned on, and the current sense amplifier (csa). the control reference for the current loops comes from the error amplifier (eamp) of the voltage loop. the pwm operation is initialized by the clock from the oscillator. the p-channel mosfet is turned on at the beginning of a pwm cycle and the current in the p-channel mosfet starts ramping up. when the sum of the csa output and the compensation slope reac hes the control reference of the current loop, the pwm comparator comp sends a signal to the pwm logic to turn off the p-channel mosfet and to turn on the n-channel mosfet. the n-mosfet remains on until the end of the pwm cycle. figure 21 shows the typical operating waveforms during the normal pwm operation. the dotted lines illustrate the sum of the slope compensation ramp and the csa output. the output voltage is regulated by controlling the reference voltage to the current loop. the band-gap circuit outputs a 0.8v reference voltage to the voltage control loop. the feedback signal comes from the fb pin. the soft-start block only affects the operation during the start-up and will be discussed separately in ?soft start-up? on page 10. the eamp is a trans conductance amplifier, which converts the voltage error signal to a current output. the voltage loop is internally compensated by a rc network. the maximum eamp voltage output is precis ely clamped to the band-gap voltage. skip mode with the mode pin connected to logic high, the device enters a pulse-skipping mode at light load to minimize the switching loss by reducing the switching frequency. figure 22 illustrates the skip mode operation. a zero-cross sensing circuit (as shown in figure 20) monitors the n-channel mosfet current for zero crossing. when it is detected to cross zero for 8 consecutive cycles, the regulat or enters the skip mode. during the 8 consecutive cycles, the inductor current could be negative. the counter is reset to zero when the sensed n- channel mosfet current does not cross zero during any cycle within the 8 consecutive cycles. once the device enters the skip mode, the pulse modulation starts being controlled by the skip comparator shown in figure 20. each pulse cycle is still synchronized by the pwm clock. the p-channel mosfet is turned on at the rising edge of clock and turned off when its current reaches 20% of the peak current limit. as the average inductor current in each cycle is higher than the average current of the load, the output voltage rises cycle over cycle. when the output voltage reaches 1.5% above its nominal voltage, the p-channel mosfet is turned off immediately and the inductor current is fully discharged to zero and stays at zero. the output voltage reduces gradually due to the load current discharging the output capacitor. when the output voltage drops to the nominal voltage, the p- channel mosfet will be turned on again, repeating the previous operations. the regulator switches to pwm mode operation when the output voltage is sensed to drop below 1.5% of its nominal voltage value. enable the enable (en) pin allows user to enable or disable the converter for purposes such as power-up sequencing. with the en pin pulled to high, the converter is enabled and the internal reference circuit wakes up first, and then the soft start-up begins. when the en pin is pulled to logic low, the converter is disabled, the p-channel mosfet is turned off immediately, and the output capacitor is discharged through internal discharge path. undervoltage lockout (uvlo) when the input voltage is below the undervoltage lock out (uvlo) threshold, the device is disabled. figure 21. pwm operation waveforms v eamp sw i l v out v csa v eamp sw i l v out v csa isl9109
10 fn6681.1 september 29, 2008 mode selection the mode pin is provided on isl9109 to select the operation mode. when it is driv en to logic low or ground, the regulator operates in forced pwm mode. under forced pwm mode, the device remains at the fixed pwm operation (typical at 1.6mhz), regardless of if the load current is high or low. when the mode pin is driven to logic high or connected to input voltage v in , the regulator operates in either skip mode or fixed pwm mode depending on the different load conditions. overcurrent protection the overcurrent protection is provided when over load condition happens. it is realized by monitoring the csa output with the ocp comparator, as shown in figure 20. when the current at p-channel mosfet is sensed to reach the current limit, the ocp comparator is triggered to turn off the p-channel mosfet immediately. short-circuit protection as shown in figure 20, the device has a short-circuit protection (scp) comparator, which monitors the fb pin voltage for output short-circ uit protection. when the fb voltage is lower than 0.2v, t he scp comparator forces the pwm oscillator frequency to drop to 1/3 of its normal operation frequency. soft start-up the soft-start-up eliminates the inrush current during the circuit start-up. the soft-start block outputs a ramp reference to both the voltage loop and the current loop. the two ramps limit the inductor current rising speed as well as the output voltage speed so that the output voltage rises in a controlled fashion. at the very beginning of the start-up, the output voltage is less than 0.2v; hence the pwm operating frequency is 1/3 of the normal frequency. power mosfets the power mosfets are optimized to achieve better efficiency. the on-resistance for the p-channel mosfet is typically 0.16 and the typical on-resistance for the n-channel mosfet is 0.15 . low dropout operation the isl9109 features low dropout operation to maximize the battery life. when the input voltage drops to a level that the device can no longer operate un der switching regulation to maintain the output voltage, the p-channel mosfet is completely turned on (100% duty cycle). the dropout voltage under such condition is the product of the load current and the on-resistance of the p-channel mosfet. minimum required input voltage v in under this condition is the sum of output voltage plus the voltage drop cross the inductor and the p-channel mosfet switch. thermal shut down the isl9109 provides built-in thermal protection function. the thermal shutdown threshold temperature is typical +160c with typical +25c hysteresis. when the internal temperature is sensed to reac h +150c, the regulator is completely shut down and as the temperature is sensed to drop to +125c (typical), the device resumes operation starting from the soft-start-up. stby the isl9109 stby pin enables the band-gap reference. this provides a method to quickly start up the buck regulator and ensure the output voltage reaches 93% of its nominal value within 60s when the en pin is asserted. the band-gap takes typical 600s to bias up and stabilize. by asserting stby high at least 1m s prior to asserting the en, the device can provide a stable output when needed. a detailed timing diagram is shown in figure 23. standby mode is entered by asserting the en pin low while stby pin is high. to achieve the specified standby operating current, both en and stby pins must be asserted high for at least 1ms after circuit start-up, before placing the device in standby mode. figure 22. skip mode operation waveforms 8 cycles clock i l v out 0 v out_nominal 20% peak current limit 1.015*v out_nominal clock i l 0 v out 1.015*v out_nominal v out_nominal isl9109
11 fn6681.1 september 29, 2008 applications information inductor and output capacitor selection to achieve better steady state and transient response, typically a 2.2h inductor can be used. the peak-to-peak inductor current ripple can be expressed as follows in equation 1: in equation 1, usually the typical values can be used but to have a more conservative estimation; the inductance should consider the value with worst case tolerance. for switching frequency f s , the minimum f s from the ?electrical specifications? table on page 2 can be used. to select the inductor, its satura tion current rating should be at least higher than the sum of the maximum output current and half of the delta calculated fr om equation 1. another more conservative approach is to sele ct the inductor with the current rating higher than the p-channel mosfet peak current limit. another consideration is the in ductor dc resistance since it directly affects the efficiency of the converter. ideally, the inductor with the lower dc resistance should be considered to achieve higher efficiency. inductor specifications could be different from different manufacturers so please check with each manufacturer if additional information is needed. for the output capacitor, a ceramic capacitor can be used because of the low esr values, which helps to minimize the output voltage ripple. a typical value of 10f/6.3v ceramic capacitor should be enough for most of the applications and the capacitor should be x5r or x7r. input capacitor selection the main function for the input capacitor is to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switchin g current from flowing back to the battery rail. a 10f/6.3v ceramic capacitor (x5r or x7r) is a good starting point for the input capacitor selection. output voltage setting resistor selection the voltage divider resistors, r 1 and r 2 , (as shown in figure 19), set the desired output voltage value. the output voltage can be calculated using equation 2: where v fb is the feedback voltage (typically it is 0.8v). the current flowing through the voltage divider resistors can be calculated as v o /(r 1 + r 2 ), so larger resistance is desirable to minimize this current. on the other hand, the fb pin has leakage current that will cause error in the output voltage setting. the leakage current has a typical value of 0.1a. to minimize the accuracy impact on the output voltage, select the r 2 no larger than 200k . c3 (shown in figure 19) is highly recommended to be added for improving stability, and achieving better transient response. c3 should be 120pf or less to meet the 60s maximum soft-startup time when stby = 1. table 1 provides the recommended component values for some output voltage options. v in stby en band-gap v out 400s~1ms band-gap wake-up band-gap off @ en=stby=low 25s bias up 25s bias up 30s v out soft-start 30s v out soft_start 400~800s band-gap wake-up 25s bias up 400~800s v out soft-start 1ms wait figure 23. timing diagram i v o 1 v o v in --------- ? ?? ?? ?? ? lf s ? -------------------------------------- - = (eq. 1) v o v fb 1 r 1 r 2 ------ - + ?? ?? ?? ? = (eq. 2) isl9109
12 fn6681.1 september 29, 2008 layout recommendation the pcb layout is a very impor tant converter design step to make sure the designed converter works well, especially under the high current high switching frequency condition. for isl9109, the power loop is composed of the output inductor l, the output capacitor c out , the sw pin and the gnd pin. it is necessary to make the power loop as small as possible and the connecting traces among them should be direct, short and wide; the same type of traces should be used to connect the vin pin, the input capacitor c in and its ground. the switching node of the converter, the sw pin, and the traces connected to this node are very noisy, so keep the voltage feedback tr ace and other noise sensitive traces away from these noisy traces. the input capacitor should be placed as close as possible to the vin pin. the ground of the input and output capacitors should be connected as close as possible as well. the heat of the ic is mainly dissipated through the thermal pad. maximizing the copper area connected to the thermal pad is preferable. in addition, a solid ground plane is helpful for emi performance. table 1. isl9109 circuit configuration vs v out vout (v) l ( h) c2 ( f) r1 (k ) c3 (pf) r2 (k ) 0.8 2.2 10 0 n/a 100 1.0 2.2 10 44.2 120 178 1.2 2.2 10 80.6 120 162 1.5 2.2 10 84.5 100 97.6 1.8 2.2 10 100 100 80.6 2.5 2.2 10 100 100 47.5 2.8 2.2 10 100 100 40.2 3.3 2.2 10 102 100 32.4 isl9109
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6681.1 september 29, 2008 isl9109 dual flat no-lead plastic package (dfn) // nx (b) section "c-c" 5 (a1) bottom view a 6 area index c c 0.10 0.08 side view 0.15 2x e a b c 0.15 d top view cb 2x 6 8 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 5 0.10 8 7 d2 b a m c n-1 12 plane seating c a a3 nx b d2/2 nx k for even terminal/side terminal tip c l e l c c l8.2x3 8 lead dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a3 0.20 ref - b 0.20 0.25 0.32 5,8 d 2.00 bsc - d2 1.50 1.65 1.75 7,8 e 3.00 bsc - e2 1.65 1.80 1.90 7,8 e 0.50 bsc - k0.20 - - - l 0.30 0.40 0.50 8 n 8 2 nd 4 3 rev. 0 6/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are prov ided to assist with pcb land pattern design efforts, see intersil technical brief tb389.

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